Data mining based prediction paradigm and its applications in design automation

Abstract form only given. This talk will review several key challenges in design automation, including areas such as pre-silicon functional verification, design-silicon timing correlation, test cost and quality and describe data mining technologies to implement a prediction platform that provides unique solutions to cover these challenges. Results based on industrial cases will be discussed and other potential applications in design automation will be explained. In the functional verification space, we will demonstrate an iterative learning framework for reducing simulation costs and improving coverage. This framework is based on two learning components: a novelty test detector and a rule extractor. The novelty test detector is a test selection mechanism that analyzes the tests, produced by the RTPG tool, prior to simulation and identifies the tests that are more likely to hit coverage holes. The rule extractor learns from novel tests identified by novelty detection. The learning is used to refine the test generation process, so the resulting tests programs are more likely to hit coverage holes. The learning framework was evaluated using the simulation infrastructure for a commercial 64-bit, multi-thread micro- processor built in a 28nm node. Based on the evaluation of toggle coverage for the complex fixed integer unit, we demonstrate the ability to reduce the number of test programs by 95%. In addition, we also demonstrate the ability to extract rules from novel test programs. These rules are used to refine test generation, where the resulting tests hit additional known coverage holes. In design-silicon timing correlation, we will show a framework for analyzing design and test data for extracting knowledge that explains unexpected test results. This framework is evaluated using silicon measurements and design data from 30 high-performance dual-core SOCs. Over 2100 paths were measured on each part. For this design, the path measurements behaved differently than the- expected values determined by the STA tools as one cluster of paths performed better than expected while another cluster performed worse. Based on the evaluation of this framework, we demonstrate the ability to explain the fast and slow paths by generating simple reasons using the test data. These rules indicate that there is a design issue with a memory controller interface wrapper and these findings were later validated by domain experts. In the parametric tests space, we will show two different parametric tests analysis frameworks for reducing tests costs and improve test quality. The first framework will demonstrate the ability to learn a predictive models from the parametric test data to predict parts that are likely-to- fail after the entire burn-in cycle. This learning framework was evaluated using 8 lots of test data from a burn-in reduction experiment performed on a 3-axis accelerometer. Each lot contains 9k dies and over 500 parametric tests were performed on each device after 10, 24 and 48 hours of burn-in. Based on the evaluation, we demonstrate the ability to identify a large group of parts, ~98% of the total population, that do not require additional burn-in after 10 hours. This suggests that it is possible to save up to 78% in burn-in costs as we can reduce the burn-in time by a factor of 4.8 for most of the parts. The remaining 2% of parts are more susceptible to failing, where this small population includes all parts that fail after the entire burn-in cycle. The second framework will demonstrate the ability to learn from the parametric wafer test data of known customer return and apply these models to seen parts that will become field failures in the future. The learning framework was evaluated using 48 lots wafer probe test data for a high quality SoC from the automotive market. Each lot contained over 12k passing dies and one customer return. More than 1000 parametric tests were performed on each device. The evaluation was formatted in a realisti