An 88-dB Max-SFDR 12-bit SAR ADC With Speed-Enhanced ADEC and Dual Registers

A 12-bit 3-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) was implemented with a modified addition-only digital error correction (ADEC) and a dual-register-based DAC control as speed-enhancement techniques. The proposed speed-enhanced ADEC (SE-ADEC) scheme employs designated capacitors for redundancy-related DAC operation and thus eliminates MUX stages from the DAC control logic. Further speed enhancement is achieved by the dual-register structure that eliminates the entire DAC switching logic. The prototype ADC was fabricated in a 0.35- μm CMOS process utilizing only thick gate transistors with a minimum gate length of 0.5 μm. With a highly linear capacitor DAC design, the prototype ADC achieves 0.38 LSB INL without calibration. The measured spurious-free dynamic range and signal-to-noise and distortion ratio (SNDR) at a low-frequency operation of 250 kS/s are 88 and 68 dB, respectively. At a sample rate of 3 MS/s, the ADC achieves a peak SNDR of 64 dB with a total power dissipation of 1.23 mW under a 2.3-V supply. The FOM_Nyq is a 368-fJ/conversion-step.