Title :
RASP: A General Logic Synthesis System for SRAM-Based FPGAs
Author :
Cong, Jason ; Peck, John ; Ding, Yuzheng
Author_Institution :
University of California, Los Angeles
Abstract :
In this paper, we present a general synthesis system for SRAM-based FPGAs named RASP. RASP consists of a core with a set of synthesis and optimization algorithms for technology independent logic synthesis and technology mapping for generating generic look-up tables (LUTs), together with a set of architecture-specific technology mapping routines to map the generic LUT network to programmable logic blocks (PLBs) for various SRAM-based FPGA architectures. Via a set of design representation converter routines, these architecture-independent and dependent synthesis algorithms are easily linked, and the entire system is seamlessly integrated into the design flow of commercial FPGA design systems. As a result, RASP can produce highly optimized designs for various SRAM-based FPGA architectures, and can be quickly adapted for new SRAM-based FPGA architectures. We compare RASP performance with that of several commercial synthesis systems on the MCNC logic synthesis benchmarks and a video compressor/decompressor. For almost all cases, RASP produces mapping solutions with significantly smaller critical path delay after place and route than current commercial synthesis systems.
Keywords :
Algorithm design and analysis; Computer science; Design optimization; Field programmable gate arrays; Network synthesis; Programmable logic arrays; Programmable logic devices; Prototypes; Table lookup; Video compression;
Conference_Titel :
Field-Programmable Gate Arrays, 1996. FPGA '96. Proceedings of the 1996 ACM Fourth International Symposium on
Print_ISBN :
0-7695-2576-8
DOI :
10.1109/FPGA.1996.242541