Stepwise refinement of behavioral VHDL specifications by separation of synchronization and functionality

We present a new method of behavioral modeling consisting of separation of synchronization and functionality. In this way incomplete specification and incremental refinement can be performed to reduce the modeling effort in early design stages. Compared to known methods our approach allows early cycle based analysis to select appropriate architectures and to perform parallel/serial tradeoff. Due to the separation of synchronization and functionality the datapath can be developed independently of the controller and thus enables concurrent engineering. Another important characteristic is the reuse friendly architecture proposed in this paper