Measuring HDL-based design productivity: an experimental comparison

Author

Joshi, Makarand ; Kim, Hyongsop ; Kobayashi, Hideaki

Author_Institution

Dept. of Electr. & Comput. Eng., South Carolina Univ., Columbia, SC, USA

fYear

1995

fDate

27-29 Mar 1995

Firstpage

44

Lastpage

48

Abstract

Two process models for top-down HDL-based design are developed in order to measure HDL-based design productivity. A sorting algorithm is used as a benchmark to experience various design activities in HDL entry and mixed entry design process models. We measure the effort (time) required for each design activity and analyze the “effort-distribution” over various design activities. We also discuss the resources that are essential to perform each design activity. These experiments the applicability of “effort-distribution analysis” to enhance design productivity in real life design projects

Keywords

hardware description languages; human resource management; logic CAD; sorting; HDL entry design process models; HDL-based design productivity measurement; design activities; effort-distribution analysis; mixed entry design process models; real life design projects; resources; sorting algorithm; top-down HDL-based design; Algorithm design and analysis; Costs; Electric variables measurement; Electronic design automation and methodology; Hardware design languages; Logic; Process design; Productivity; Sorting; Time measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Verilog HDL Conference, 1995. Proceedings., 1995 IEEE International

Conference_Location

Santa Cruz, CA

Print_ISBN

0-8186-7082-7

Type

conf

DOI

10.1109/IVC.1995.512467

Filename

512467