FPGA-based digit-serial complex number multiplier-accumulator

Author

Sansaloni, T. ; Valls, J. ; Parhi, K.K.

Author_Institution

Dipt. de Ing. Electron., Univ. Politecnica de Valencia, Spain

Volume

4

fYear

2000

fDate

2000

Firstpage

585

Abstract

This paper presents a FPGA implementation of digit-serial complex number Multiplier-Accumulators (CMACs) based on Booth recoding techniques and carry save (CS) adders. The complex number Multiplier-Accumulators can be pipelined at LUT-level. An efficient mapping of the Booth recoding and the partial product generation is presented which results in a logic depth reduction. The combination of 5-3 and 4-3 converters in the CS structure and the utilization of ripple carry adder (RCA) trees lead to a minimum area requirement

Keywords

adders; carry logic; field programmable gate arrays; multiplying circuits; pipeline arithmetic; 4-3 converter; 5-3 converter; Booth recoding techniques; FPGA-based digit-serial complex number multiplier-accumulator; LUT-level pipelining; carry save adders; complex number multiplier-accumulators; logic depth reduction; minimum area requirement; partial product generation; ripple carry adder trees; Adders; Arithmetic; Digital signal processing; Field programmable gate arrays; Finite impulse response filter; IIR filters; Programmable logic devices; Sampling methods; Throughput; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on

Conference_Location

Geneva

Print_ISBN

0-7803-5482-6

Type

conf

DOI

10.1109/ISCAS.2000.858819

Filename

858819