• DocumentCode
    2277820
  • Title

    An adaptive modular reduction based error-detection algorithm

  • Author

    Yin, Zuobiao ; Yang, Wenhui ; Xiong, Jianping

  • Author_Institution
    Dept. of Precision Instrum. & Mechanology, Tsinghua Univ., Beijing, China
  • fYear
    2012
  • fDate
    10-11 May 2012
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    In this paper, an adaptive modular reduction based error-detection algorithm is proposed, it is based on the research of the modular reduction model and the missing rate of residue code. In the proposed method, more than one moduli are used to detect the input before they being sent into the functional logic, then the best modulus is chosen accordingly to optimizing the error detection performance. The simulation shows that, for the frequently-used unit in signal processing, such as addition and multiplication, fault missing rate of the proposed method is lower than that of the regular method under the same circuit size. And the cost of the detection branch in the proposed method is lower than that in the regular method under the same fault missing rate.
  • Keywords
    error detection; field programmable gate arrays; residue codes; signal processing; FPGA; SEU; adaptive modular reduction based error-detection algorithm; addition; circuit size; detection branch cost; error detection performance; fault missing rate; functional logic; modular reduction model; multiplication; residue code missing rate; signal processing; Circuit faults; Computer architecture; Field programmable gate arrays; Redundancy; Satellites; Single event upset; Tunneling magnetoresistance; FPGA; SEU; modular reduction;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    High Speed Intelligent Communication Forum (HSIC), 2012 4th International
  • Conference_Location
    Nanjing, Jiangsu
  • Print_ISBN
    978-1-4673-0678-2
  • Electronic_ISBN
    978-1-4673-0676-8
  • Type

    conf

  • DOI
    10.1109/HSIC.2012.6212967
  • Filename
    6212967