The design and implementation of DCT/IDCT chip with novel architecture

Author

Cheng, Kuo-Hsing ; Huang, Chih-Sheng ; Lin, Chun-Pin

Author_Institution

Dept. of Electr. Eng., Tamkang Univ., Tamsui, Taiwan

Volume

4

fYear

2000

fDate

2000

Firstpage

741

Abstract

In the paper, an efficient VLSI architecture for a 8×8 two-dimensional discrete cosine transform and inverse discrete cosine transform (2-D DCT/IDCT) with a new 1-D DCT/IDCT algorithm is presented. The proposed new algorithm makes sure all coefficients are positive to simplify the design of multipliers and the coefficients have less round-off error than Lee´s algorithm. For computing 2-D DCT/IDCT, the row-column decomposition method is used, and the design of 1-D DCT/IDCT requires only 9 multipliers and 21 adders/subtractors. This chip is synthesized with 0.6 μm standard cell library and 1P3M CMOS technology, and it can be operated up to 100 MHz

Keywords

CMOS digital integrated circuits; adders; cellular arrays; digital signal processing chips; discrete cosine transforms; multiplying circuits; roundoff errors; 0.6 micron; 100 MHz; 1P3M CMOS technology; DCT; IDCT; VLSI architecture; adders; inverse discrete cosine transform; multipliers; round-off error; row-column decomposition method; standard cell library; subtractors; two-dimensional discrete cosine transform; Algorithm design and analysis; CMOS technology; Costs; Discrete cosine transforms; Electronic mail; Equations; Flow graphs; Hardware; Roundoff errors; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on

Conference_Location

Geneva

Print_ISBN

0-7803-5482-6

Type

conf

DOI

10.1109/ISCAS.2000.858858

Filename

858858