DocumentCode
227829
Title
Performance and scalability of parallel PIC and fluid codes on Xeon Phi based supercomputers
Author
Hallman, Eric J. ; Beckwith, Kristian C. ; Stoltz, Peter
Author_Institution
Tech-X Corp., Boulder, CO, USA
fYear
2014
fDate
25-29 May 2014
Firstpage
1
Lastpage
1
Abstract
Summary form only given. We present results from performance tests for 3 highly parallel numerical simulation codes on the Texas Advanced Computing Center´s Stampede Supercomputer. Stampede utilizes the Intel Xeon Phi architecture, which includes the Many Integrated Core (MIC) co-processors, programmed with a standard x86 instruction set.
Keywords
mainframes; parallel machines; MIC; Texas advanced computing center stampede supercomputer; Xeon Phi architecture; Xeon Phi based supercomputers; co-processors; fluid codes; many integrated core; numerical simulation; parallel PIC performance; parallel PIC scalability; standard x86 instruction set; Computer architecture; Fluids; Microwave integrated circuits; Numerical simulation; Resource management; Scalability; Supercomputers;
fLanguage
English
Publisher
ieee
Conference_Titel
Plasma Sciences (ICOPS) held with 2014 IEEE International Conference on High-Power Particle Beams (BEAMS), 2014 IEEE 41st International Conference on
Conference_Location
Washington, DC
Print_ISBN
978-1-4799-2711-1
Type
conf
DOI
10.1109/PLASMA.2014.7012560
Filename
7012560
Link To Document