DocumentCode
2279541
Title
Layout optimization of ESD protection TFO-NMOS by two-dimensional device simulation
Author
Daebin Yim ; Hyunchul Kim ; Doohun Song ; Junho Back
Author_Institution
DT Lab, ULSI Lab., Seoul, South Korea
fYear
1997
fDate
8-10 Sept. 1997
Firstpage
29
Lastpage
31
Abstract
The first-pass design methodology of ESD protection TFO-NMOS device has been developed using 2D process and device simulation. The ranges of optimum layout parameters have been suggested by investigating the current-to-failure and time-to-failure profiles extracted from 2D electro-thermal mixed-mode device simulation results.
Keywords
MOSFET; electrostatic discharge; failure analysis; protection; semiconductor device models; 2D process simulation; ESD protection TFO-NMOS; current-to-failure; first-pass design methodology; layout optimization; time-to-failure; two-dimensional electrothermal mixed-mode device simulation; Circuit simulation; Electrostatic discharge; Equations; Immune system; Laboratories; Medical simulation; Protection; Random access memory; Temperature; Thermal stresses;
fLanguage
English
Publisher
ieee
Conference_Titel
Simulation of Semiconductor Processes and Devices, 1997. SISPAD '97., 1997 International Conference on
Conference_Location
Cambridge, MA, USA
Print_ISBN
0-7803-3775-1
Type
conf
DOI
10.1109/SISPAD.1997.621328
Filename
621328
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