DocumentCode :
2281361
Title :
FPGA implementation of the timing synchronization in preamble based OFDM system
Author :
Gu, Y.J. ; Li, Y. ; Ren, W. ; Chen, K.S.
Author_Institution :
Zhejiang Univ., Hangzhou
fYear :
2005
fDate :
15-17 Nov. 2005
Lastpage :
4
Abstract :
Orthogonal frequency division multiplexing (OFDM) is an effective modulation technique for high-rate transmission over frequency selective fading channels. However, just because of its orthogonality, OFDM systems are also extremely sensitive and vulnerable to synchronization errors. In this paper, we investigate a scheme especially for symbol synchronization utilizing the special training structure, which can be used in preamble-based OFDM system. Without loss the generality, IEEE 802.11a WLAN system will be researched as the model. The algorithms of match filter and cyclic prefix (CP) are combined to achieve good symbol timing synchronization. The former algorithm is to determine the short training symbol´s precise end of the burst transmission, and then the latter algorithm will confirm the valid data of data symbols. At last, we present the timing synchronization´s FPGA implementation
Keywords :
OFDM modulation; fading channels; field programmable gate arrays; matched filters; synchronisation; wireless LAN; FPGA; IEEE 802.11a WLAN system; OFDM system; cyclic prefix; frequency selective fading channels; match filter; orthogonal frequency division multiplexing; timing synchronization; FPGA; Synchronization; cyclic prefix; match filter;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Mobile Technology, Applications and Systems, 2005 2nd International Conference on
Conference_Location :
Guangzhou
Print_ISBN :
981-05-4573-8
Type :
conf
DOI :
10.1109/MTAS.2005.207172
Filename :
1656712
Link To Document :
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