Evaluating FPGAs: capacity and utilization

The authors present the experimental results of a study on the effective capacity of a set of field programmable gate array (FPGA) devices and the influence of different circuit types on their utilization. A practical mix of benchmark circuits were used with several different FPGAs. The results indicate that (1) optimization is necessary to effect efficient device utilization, (2) devices with built in flip-flops are not efficient in implementing combinational circuits, and (3) the percentage of flip-flops in a circuit should match the percentage of flip-flops in the total device to maximize gate density. A graphical model is presented to interpret these results