Hybrid CMOS - Memristor based configurable logic block design

With increasing demand for greater storage capacity and lower power consumption in memory devices, memristors have emerged as a cutting-edge alternative to transistor based circuitry. After performing a study of the various models for memristor behavior, the TEAM model was used in this paper because of its flexibility to design a hybrid CMOS-memristor based memory crossbar array. The design is substantiated with appropriate simulation results using Cadence. In addition, a lookup table carrying out the function of 1-bit full adder is implemented as an application of memristor based memory. The paper also presents the design of a configurable logic block (CLB), which can be used to fabricate a hybrid CMOS - Memristor FPGA architecture. Based on the memory design, the study evaluates the various advantages of a memristive device over the traditional CMOS approach and shows that the hybrid memory architecture is more efficient.