Data compression using Shannon-fano algorithm implemented by VHDL

In digital communication while transmit the data it is well desire that the transmitting data bits should be as minimum as possible, so to compress the data there are several technique used. In this paper we have implemented a Shannon-fano algorithm for data compression through VHDL coding. Using VHDL implementation we can easily observe that how many bits we can save or how much data gets compressed during transmission, and we can also see the encoding of the respective symbol of transmit data. In the field of data compression the Shannon-fano algorithm is used, this algorithm is also used in an implode compression method which are used in zip file or .rar format. To implement this algorithm in VHDL we use ModelSim SE 6.4 simulators and to synthesize these code Quartus-II tool has been used.