• DocumentCode
    2283552
  • Title

    Exploiting Postdominance for Speculative Parallelization

  • Author

    Agarwal, Mayank ; Malik, Kshitiz ; Woley, Kevin M. ; Stone, Sam S. ; Frank, Matthew I.

  • Author_Institution
    Coordinated Sci. Lab., Univ. of Illinois at Urbana-Champaign
  • fYear
    2007
  • fDate
    10-14 Feb. 2007
  • Firstpage
    295
  • Lastpage
    305
  • Abstract
    Task-selection policies are critical to the performance of any architecture that uses speculation to extract parallel tasks from a sequential thread. This paper demonstrates that the immediate postdominators of conditional branches provide a larger set of parallel tasks than existing task-selection heuristics, which are limited to programming language constructs (such as loops or procedure calls). Our evaluation shows that postdominance-based task selection achieves, on average, more than double the speedup of the best individual heuristic, and 33% more speedup than the best combination of heuristics. The specific contributions of this paper include, first, a description of task selection based on immediate post-dominance for a system that speculatively creates tasks. Second, our experimental evaluation demonstrates that existing task-selection heuristics based on loops, procedure calls, and if-else statements are all subsumed by compiler-generated immediate postdominators. Finally, by demonstrating that dynamic reconvergence prediction closely approximates immediate postdominator analysis, we show that the notion of immediate postdominators may also be useful in constructing dynamic task selection mechanisms
  • Keywords
    parallel processing; program compilers; program control structures; task analysis; compiler; dynamic reconvergence prediction; if-else statements; immediate postdominators; loops; parallel tasks; postdominance-based task selection; procedure calls; programming language constructs; sequential thread; speculative parallelization; Centralized control; Computer languages; Data mining; Flow graphs; Performance analysis; Program processors; Tree graphs; Yarn;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    High Performance Computer Architecture, 2007. HPCA 2007. IEEE 13th International Symposium on
  • Conference_Location
    Scottsdale, AZ
  • Print_ISBN
    1-4244-0805-9
  • Electronic_ISBN
    1-4244-0805-9
  • Type

    conf

  • DOI
    10.1109/HPCA.2007.346207
  • Filename
    4147670