Title :
FA 18.4: a phase-tolerant 3.8 GB/s data-communication router for a multiprocessor supercomputer backplane
Author :
Reese, E.A. ; Wilson, H. ; Nedwek, D. ; Jex, J. ; Khaira, M. ; Burton, T. ; Nag, P. ; Kumar, H. ; Dike, C. ; Finan, D. ; Haycock, M.
Author_Institution :
Intel Corp., Hillsboro, OR, USA
Abstract :
Recent parallel processor supercomputer designs use an active backplane of routers to form the interconnections between processing elements. Today, high-bandwidth interconnect systems capable of scaling to configurations with more than 500 processing nodes tend to use self-timed designs. This avoids clock distribution problems seen in large phase-sensitive synchronous systems. The BiCMOS routing component described in this paper employs 200 MHz clocked communication for large scalable parallel-processor supercomputer systems. This scheme eliminates need for clock edges to be phase-aligned across the clock distribution network. Additionally, router inputs accept data at any phase relationship to the receiving router internal clock.<>
Keywords :
BiCMOS integrated circuits; clocks; data communication equipment; multiprocessor interconnection networks; network routing; parallel machines; system buses; 200 MHz; 3.8 GB/s; BiCMOS routing component; FA 18.4; active backplane; clock distribution problems; clock edges; clocked communication; high-bandwidth interconnect systems; multiprocessor supercomputer backplane; phase relationship; phase-tolerant data-communication router; processing element interconnections; processor configurations; receiving router internal clock; scalable parallel processor; scaling; self-timed designs; Backplanes; Circuits; Clocks; Delay effects; Frequency; Levee; Nearest neighbor searches; Routing; Supercomputers; Synchronization;
Conference_Titel :
Solid-State Circuits Conference, 1994. Digest of Technical Papers. 41st ISSCC., 1994 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-1844-7
DOI :
10.1109/ISSCC.1994.344634
