A 220 MHz pipelined 16 Mb BiCMOS SRAM with PLL proportional self-timing generator

Author

Nakamura, K. ; Kuhara, S. ; Kimura, T. ; Takada, M. ; Suzuki, H. ; Yoshida, H. ; Yamazaki, T.

Author_Institution

NEC Corp., Kanagawa, Japan

fYear

1994

fDate

16-18 Feb. 1994

Firstpage

258

Lastpage

259

Abstract

This 512 kw/spl times/8 b/spl times/4 way synchronous BiCMOS SRAM uses a 2-stage wave-pipeline scheme, a PLL self-timing generator, and a 0.4 /spl mu/m BiCMOS process to achieve 220 MHz fully-random read/write operations with a GTL I/O interface. Circuit approaches include 1) zigzag double word-line, 2) centralized bit-line load layout, and 3) phase-locked-loop (PLL) with a multi-stage-tapped (MST) ring oscillator that generates not only a de-skewed internal clock, but also a clock-cycle-proportional pulse and a clock-edge-lookahead pulse.<>

Keywords

BiCMOS integrated circuits; SRAM chips; phase-locked loops; pipeline processing; synchronisation; 0.4 micron; 16 Mbit; 2-stage wave-pipeline scheme; 220 MHz; BiCMOS SRAM; GTL I/O interface; PLL self-timing generator; centralized bit-line load layout; clock-cycle-proportional pulse; clock-edge-lookahead pulse; deskewed internal clock; multistage-tapped ring oscillator; phase-locked-loop; synchronous static RAM; zigzag double word-line; BiCMOS integrated circuits; Clocks; Delay effects; MOSFETs; Phase locked loops; Pipelines; Pulse circuits; Random access memory; Synchronous generators; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1994. Digest of Technical Papers. 41st ISSCC., 1994 IEEE International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-1844-7

Type

conf

DOI

10.1109/ISSCC.1994.344650

Filename

344650