A novel hybrid multiple mode power gating

Leakage power is a serious problem in CMOS technology and power gating offers a standard solution to this problem with a small penalty in performance. As technology moves into the deep-sub micron region, the effect of leakage power will be more. This paper propose a novel hybrid power gating technique with multiple sleep modes, each mode represents the trade-off between the wakeup overhead and leakage savings. The multiple sleep modes reduces the wakeup power penalty. This novel hybrid power gating shows a large static power reduction than existing multimode technique. The design of hybrid power gating technology in 8 bit ALU was done in Cadence Virtuoso tool.