FPGA implementation of low area and delay efficient Adaptive Filter using Distributed Arithmetic

This brief presents a pipelined architecture for low-area and delay-efficient design on FPGA for Adaptive FIR Filter using Distributed Arithmetic. The design of Adaptive FIR Filter involves more multipliers and adders (MAC) which consumes more area and power. The Distributed Arithmetic (DA) logic replaces the MAC operation of FIR filter into a bit serial nature of look up table shift and add operation. Hence the implementation of adaptive FIR filter using DA is less expansive and delay efficient method. This paper presents comparative study of FPGA resource analysis and synthesis reports of Adaptive FIR filter using MAC and DA based Adaptive FIR filter.