A sixth-order triple-loop sigma-delta CMOS ADC with 90 dB SNR and 100 kHz bandwidth

Author

Dedic, I.

Author_Institution

European Mixed-Signal ASIC Design Center, Fujitsu Microelectron. Ltd., Maidenhead, UK

fYear

1994

fDate

16-18 Feb. 1994

Firstpage

188

Lastpage

189

Abstract

The conversion rate of high-resolution wideband sigma-delta ADCs is limited by need for high oversampling ratio, typically 64 or more, for rejection of quantization noise. These rates lead to high amplifier power, large power-hungry digital filters, and difficult-to-drive signal and reference inputs. For 16b performance with low oversampling ratio it is necessary to use high-order noise shaping and/or multi-level quantizers and DACs, both leading to problems in design or manufacture if realized directly. The ADC described here consists of three cascaded second-order three-level loops giving a sixth-order noise-shaping function without linearity and stability problems from component mismatch or quantizer overload.<>

Keywords

CMOS integrated circuits; analogue-digital conversion; cascade networks; delta modulation; linear integrated circuits; 100 kHz; 16 bit; CMOS; amplifier power; cascaded second-order three-level loops; conversion rate; digital filters; noise shaping; oversampling ratio; quantization noise; sixth-order triple-loop sigma-delta ADC; Broadband amplifiers; Delta-sigma modulation; Digital filters; High power amplifiers; Manufacturing; Multi-stage noise shaping; Noise shaping; Quantization; Signal to noise ratio; Wideband;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1994. Digest of Technical Papers. 41st ISSCC., 1994 IEEE International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-1844-7

Type

conf

DOI

10.1109/ISSCC.1994.344676

Filename

344676