DocumentCode
2285546
Title
Novel structures for serial multiplication over the finite field GF(2m)
Author
Mekhallalati, M.C. ; Ashur, A.S.
Author_Institution
Dept. of Electr. & Electron. Eng., Nottingham Univ., UK
fYear
1996
fDate
30 Oct-1 Nov 1996
Firstpage
65
Lastpage
74
Abstract
Two novel uni-directional systolic structures for serial multiplication over the finite field GF(2m) are presented. The architecture of the new structures posses features of regularity, modularity, and uni-directional data flow. One of the new structures is a serial-parallel structure, whereas the other structure is a fully serial one. Both structures consist of (m/2) novel cells. Due to the novel cells architectures of the new structures, the initial delay (i.e. the number of cycles required to obtain the first output) and the latency (i.e. the number of cycles required to complete the multiplication process) are decreased by 25% and 17% respectively. Also, the number of latches of the new structures are reduced by more than 20% when compared to existing uni-directional serial-parallel structures
Keywords
Galois fields; digital arithmetic; digital signal processing chips; multiplying circuits; systolic arrays; digital signal processing; error control coding; finite field; initial delay; latches; latency; modular architecture; regular architecture; serial multiplication; serial structure; serial-parallel structure; unidirectional data flow; unidirectional systolic structures; Computer applications; Cryptographic protocols; Cryptography; Delay; Digital signal processing; Distributed Bragg reflectors; Error correction; Galois fields; Polynomials; Signal generators;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Signal Processing, IX, 1996., [Workshop on]
Conference_Location
San Francisco, CA
Print_ISBN
0-7803-3134-6
Type
conf
DOI
10.1109/VLSISP.1996.558302
Filename
558302
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