ASIC implementation of a high speed error tolerant adder

Adders are inevitable components in digital system design and embedded applications. The performance parameters of adders play a vital role in maximizing the efficiency of these applications. The necessity of error-tolerant circuits was prefigured in the 2003 International Technology Roadmap for Semiconductors (ITRS). Earlier works that deal with error-tolerance include flagged prefix adder and fixed width multiplier that have failed to achieve significant progress in their performance. The error tolerant adder can enhance the speed of computation by compromising on accuracy. This paper presents high speed error tolerant adder. The results show that proposed ETA attains 16% improvement in speed compared to its counterpart. The design was implemented using 180nm TSMC library.