Title :
Performance analysis of maximum length LFSR and BBS method for cryptographic application
Author :
Abinaya, N.S. ; Prakasam, P.
Author_Institution :
VLSI Design, Tagore Inst. of Eng. & Technol., Attur, India
Abstract :
Today cryptography is an integral part of our lives. PRNG´s are used in modern cryptography. The maximal length PN-sequence (m-sequence) is the best known best-described PN-sequence whose length is equal to its period. Various PN-codes can be generated using Linear Feedback Shift Register (LFSR). The generator polynomial provides the necessary feedback taps for the LFSR circuit. The implementation of the LFSR circuit with VLSI technology makes it useful in low-power communication system design. This paper presents the performance comparison of 4 bit LFSR method with BBS and the reported results show that LFSR is more suitable for cryptographic application.
Keywords :
VLSI; cryptography; m-sequences; polynomials; random number generation; shift registers; 4 bit LFSR method; BBS; LFSR circuit; PN-codes; PRNG; VLSI technology; best-described PN-sequence; cryptographic application; cryptography; generator polynomial; linear feedback shift register; low-power communication system design; m-sequence; maximal length PN-sequence; word length 4 bit; Ciphers; Clocks; Data collection; Logic gates; Polynomials; Very large scale integration; Cryptography; Linear Feedback Shift Register; Low power VLSI;
Conference_Titel :
Electronics and Communication Systems (ICECS), 2014 International Conference on
Conference_Location :
Coimbatore
Print_ISBN :
978-1-4799-2321-2
DOI :
10.1109/ECS.2014.6892699
