Implementation of clock gating technique and performing power analysis for processor engine (ALU) in network processors

Power dissipation is a bottleneck in the design of high speed synchronous systems operating at high frequency. Thus, clock signals have been a great source of power dissipation because of high frequency and heavy packet traffic in the network routers. Clock signals do not carry any information used for computation and only used for synchronization, but, the power dissipated is significant. In a Network Processor (NP) consisting of more than one processing elements (PE), not all are functioning at the same time, but connected to the clock signal dissipate power. Hence, the clock gating (CG) technique can to applied to these PEs. In this paper as a initial step to the design of such PEs the CG is applied to a 16-bit ALU. The design is simulated using QuestaSim power aware simulator, implemented and synthesized using Precision synthesis tool on a 45nm Spartan 6 FPGA. Power analysis is carried out using Xilinx XPower analyzer. Reduction in Clock and dynamic power is observed for lower frequencies but for high frequency the target device has the limitation. The design is optimized for power and area.