DocumentCode
2289606
Title
CUDA-based acceleration of post deblocking filter
Author
Liu, Ting ; Chen, Chunchun ; Yang, Eryan.
Author_Institution
Sch. of Commun. & Inf. Eng., Shanghai Univ., Shanghai, China
fYear
2011
fDate
6-7 Oct. 2011
Firstpage
53
Lastpage
56
Abstract
In this paper, an accelerated post deblocking filter algorithm based on CUDA (Computer unifiled device architecture) technology is proposed. The algorithm is used to remove block artifacts and improves the visual quality. It is computationally intensive and usually requires high speed processors to run in real time. A commonly efficient way can be obtained using the DSP (Digital Signal Processing) or other hardware resources. Here, we put forward a software solution method. Using NVIDIA´s CUDA technology, we save more hardware resources and make up the low programmability of hardware. CUDA technology assists GPU (Graphics Processing Unit) to work for CPU for large computation. In the experiment, a frame was picked up from JM (Joint Model) decoder stream and filtered by the improved algorithm. Without changing subjective quality, the result shows that the processing time saved 5.69 times than CPU.
Keywords
coprocessors; decoding; filters; CUDA based acceleration; GPU; NVIDIA CUDA technology; accelerated post deblocking filter algorithm; computer unifiled device architecture technology; graphics processing unit; joint model decoder stream; software solution method; Algorithm design and analysis; Educational institutions; Filtering; Filtering algorithms; Graphics processing unit; Instruction sets; Streaming media;
fLanguage
English
Publisher
ieee
Conference_Titel
Microelectronics and Electronics (PrimeAsia), 2011 Asia Pacific Conference on Postgraduate Research in
Conference_Location
Macau
ISSN
2159-2144
Print_ISBN
978-1-4577-1608-9
Type
conf
DOI
10.1109/PrimeAsia.2011.6075069
Filename
6075069
Link To Document