Low power technology mapping by hiding high-transition paths in invisible edges for LUT-based FPGAs

Considering that the connection switches possessing large resistance and capacitance in lookup-table-based (LUT-based) Field Programmable Gate Array (FPGA) routing channels consume a great portion of total power, a power-saving technology mapping algorithm is proposed tending to reduce the transition density on “visible” edges of the mapped logic circuits by hiding the paths with high transition activity in “invisible” edges. Meanwhile, the number of LUTs is also kept optimally small compared to prior technology mapping method. Finally, detailed simulation results of certain benchmark circuits are presented to verify the performance of the proposed algorithm