• DocumentCode
    2291280
  • Title

    Video applications on hyper-threading technology

  • Author

    Chen, Yen-Kuang ; Holliman, Matthew ; Debes, Eric

  • Author_Institution
    Intel Labs., Santa Clara, CA, USA
  • Volume
    2
  • fYear
    2002
  • fDate
    2002
  • Firstpage
    193
  • Abstract
    This paper characterizes selected workloads of multimedia applications on current superscalar architectures, and then it characterizes the same workloads on Intel hyper-threading technology. This technology enables multiple threads to run in parallel on a processor, by interleaving instructions from different threads in the pipeline. The workloads, including video encoding, decoding, and watermark detection, are optimized for the Intel Pentium 4 processor. Even if the workloads are very well optimized for the Pentium 4 processor, most of the modules in these well-optimized workloads cannot fully utilize all the execution units available in the microprocessor, due to the inherently sequential constitution of the algorithms. Some of the modules are memory-bounded, while some are computation-bounded. Therefore, hyper-threading technology is a promising architecture feature that allows more CPU resources to be used at a given moment. Our goal is to provide a better explanation of the performance improvements that are possible in multimedia applications using hyper-threading technology. We demonstrate different task partition/scheduling schemes and discuss their trade-offs so that the reader can understand how to develop efficient applications on processors with hyper-threading technology.
  • Keywords
    decoding; microprocessor chips; multimedia computing; parallel architectures; pipeline processing; processor scheduling; video coding; watermarking; CPU resources; Intel hyper-threading technology; Pentium 4 microprocessor; multimedia applications; parallel processing; superscalar architectures; video decoding; video encoding; watermark detection; Computer architecture; Constitution; Decoding; Encoding; Interleaved codes; Microprocessors; Pipelines; Processor scheduling; Watermarking; Yarn;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Multimedia and Expo, 2002. ICME '02. Proceedings. 2002 IEEE International Conference on
  • Print_ISBN
    0-7803-7304-9
  • Type

    conf

  • DOI
    10.1109/ICME.2002.1035546
  • Filename
    1035546