Evaluating private vs. shared last-level caches for energy efficiency in asymmetric multi-cores

In this work we explore the tradeoffs between energy and performance for several last-level cache configurations in an asymmetric multi-core system. We show that for switching threads between cores at intervals on the order of 100k or more instructions, the performance difference is negligible when private last-level caches are used in place of shared last-level caches. Thus, last-level caches can be matched to meet the needs of their host core in order to improve energy efficiency. In particular, we show that when private last-level caches are used to maintain thread state, in conjunction with energy-saving optimizations, the energy delay product of the last-level caches can be reduced by 25% on average for switching frequencies on the order of an operating system scheduling quanta-e.g., every 1 million instructions. Further, the optimizations we propose, such as power-state-aware data forwarding, are simple to implement, and the necessary support for them is already present in most current architectures.