Processing speed improvement based on an efficient symbol decoding structure in a T-DMB software baseband receiver

Unlike the computationally intensive channel decoding part in the T-DMB baseband receiver, the symbol decoding part consists of many computationally not-intensive function blocks handling complex data. Hence, if implemented in software running on a digital signal processor (DSP) with a small on-chip memory, the symbol decoding part consumes considerable DSP processing power. To improve the processing speed of this part, we propose an efficient symbol decoding structure where data are processed on an OFDM symbol basis and in-process data buffers are reused. As a result, during the entire symbol decoding process, all in-process data are stored on the fast on-chip memory without access to the slow external memory. To further improve the processing speed by reducing the number of load and store cycles required in the symbol decoding part, several function blocks are integrated into one function block. The validity of the proposed structure is confirmed by measurements of the execution cycle number and the bit error rate on an implemented T-DMB software baseband receiver.