• DocumentCode
    2297362
  • Title

    Leading-one prediction scheme for latency improvement in single datapath floating-point adders

  • Author

    Bruguera, Javier D. ; Lang, Tomas

  • Author_Institution
    Dept. of Electron. & Comput. Eng., Santiago de Compostela Univ., Spain
  • fYear
    1998
  • fDate
    5-7 Oct 1998
  • Firstpage
    298
  • Lastpage
    305
  • Abstract
    This paper describes the design of a Leading-one Predictor (LOP) for floating-point addition, with an exact determination of the shift amount required. Previous LOP proposals produce a shift amount which might be in error by one position, so that this error has to be corrected after the addition terminates, increasing the critical path. Our design incorporates a concurrent detection of this error so that the amount of shift is corrected before the actual shift, without increasing the latency. The scheme presented here is applicable to the common case of a single datapath floating-point addition in which the output of the adder is always positive. We estimate the reduction in the critical path and the increase in area
  • Keywords
    adders; floating point arithmetic; Leading-one Predictor; critical path; floating-point adders; floating-point addition; single datapath; Added delay; Adders; Computer errors; Contracts; Detectors; Encoding; Error correction; Process design; Proposals;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Design: VLSI in Computers and Processors, 1998. ICCD '98. Proceedings. International Conference on
  • Conference_Location
    Austin, TX
  • ISSN
    1063-6404
  • Print_ISBN
    0-8186-9099-2
  • Type

    conf

  • DOI
    10.1109/ICCD.1998.727065
  • Filename
    727065