Data cache parameter measurements

We extend prior research by Saavedra and Smith on designing microbenchmarks to measure data cache parameters. Unlike Saavedra and Smith, we measure the parameters by characterizing read accesses separately from write accesses; and we do not assume that the address mapping function is a bit-selection. We can measure the cache capacity C, block size b, and associativity a; we can measure the cache-hit access time and penalty for read and write; we can determine whether a cache allocates on write; we can detect write-back and write-through policies. We present experimental results for two CPU/cache structures, a 200 MHz Pentium with MMX and a 180 MHz Pentium Pro