Title :
Low-power radix-8 divider
Author :
Nannarelli, Alberto ; Lang, Tomas
Author_Institution :
Dept. of Electr. & Comput. Eng., California Univ., Irvine, CA, USA
Abstract :
This work describes the design of a double-precision radix-8 divider. Low-power techniques are applied in the design of the unit, and energy-delay tradeoffs considered. The energy dissipation in the divider can be reduced by up to 70% with respect to a standard implementation not optimized for energy, without penalizing the latency. The radix-8 divider is compared with the one obtained by overlapping three radix-2 stages and with a radix-4 divider. Results show that the latency of our divider is similar to that of the divider with overlapped stages, but the area is smaller. The speed-up of the radix-8 over the radix-4 is about 20% and the energy dissipated to complete a division is almost the same, although the area of the radix-8 is 50% larger
Keywords :
digital arithmetic; dividing circuits; double-precision radix-8 divider; energy dissipation; energy-delay tradeoffs; latency; low-power radix-8 divider; Circuit testing; Delay; Design engineering; Energy consumption; Energy dissipation; Hardware; Identity-based encryption; Lapping; Libraries; Postal services;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1998. ICCD '98. Proceedings. International Conference on
Conference_Location :
Austin, TX
Print_ISBN :
0-8186-9099-2
DOI :
10.1109/ICCD.1998.727084