DCP: an algorithm for datapath/control partitioning of synthesizable RTL models

Currently, the majority of ASIC and custom chip implementations go through a process by which a cycle-accurate synthesizable RTL model is refined into an RT/gate-level model that has been partitioned into datapath and control. This partitioning is usually done manually. This paper describes an algorithm for automatic datapath/control decomposition of synthesizable RTL models based on communication and area considerations. The partitioning results match the decisions made by human designers. Automatic partitioning provides a foundation for better RT-level analysis such as more accurate high-level area and timing estimates for designs implemented with deep submicron IC technologies. Tools that operate at the RT-level are becoming increasingly important as integration levels and design complexity continue to rise. We demonstrate one application of automatic datapath/control partitioning by using DCP to compute significantly more accurate area estimates in much less time