A fractal compaction algorithm for efficient power estimation

A fast and accurate power estimation tool is essential for low power design. In order to make power estimation through simulation both fast and accurate, one approach is to generate a compact, representative vector set with similar switching behavior as the original larger vector set. In this paper, we present an algorithm based on fractal concepts for generating compact vector sets. The fractal approach exploits correlation in toggle distribution of the circuit´s internal nodes for compaction. Tests were carried out on combinational circuits from the ISCA85 benchmark suite with both uncorrelated and correlated primary input vector sets each of size 4000. For the uncorrelated vectors, the compaction ratio was 65X(max) and 38X(avg) while the error in estimation was 2.4(max) and 2.06%(avg). For inputs with spatial and temporal correlation of 0.5, the compaction was 125X(max) and 50X(avg) with 4.86%(max) and 3.38%(avg) error in estimation