A Synthesis Flow for Sequential Reversible Circuits

In this paper, a synthesis flow for sequential reversible circuits is proposed. In particular, a methodology is introduced which transforms a finite state machine into a Boolean function representing the sequential behavior. Having that, any combinational synthesis approach can be exploited in order to perform the actual synthesis. Heuristics ensure that encodings for the states are applied which keep the costs of the resulting circuits low. Experiments show the applicability of the approach.