Title :
Multiple-Valued Time-Based Architecture for Serial Communication Links
Author :
Rashdan, Mostafa ; Haslett, James ; Maundy, Brent
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Calgary, Calgary, AB, Canada
Abstract :
A new multi-level differential-time-signaling (DTS) architecture for serial communication links is presented in this paper. The proposed system concentrates the transmitted signal energy in a smaller bandwidth than conventional architectures, allowing higher data rates for a given channel, and uses simple circuitry compared to other serial links, resulting in less power consumption and chip area. A 6-bit 3Gb/s three-level DTS link has been simulated using Cadence tools in a mixed-signal 90nm CMOS process. The eye diagrams of the transmitted signal and of the received signal at the end of a 40-inch FR-4 channel are presented. The spectral energy content in the transmitted signal is compared to our two-level DTS architecture and to the standard Serializer/Deserializer (SerDes) architecture to illustrate the advantages.
Keywords :
CMOS logic circuits; flip-flops; telecommunication links; Cadence tools; D-type flip-flop; FR-4 channel; SerDes architecture; bit rate 3 Gbit/s; chip area; mixed-signal CMOS process; multilevel DTS architecture; multilevel differential-time-signaling architecture; multiple-valued time-based architecture; power consumption; serial communication links; serializer-deserializer architecture; size 40 inch; size 90 nm; spectral energy content; three-level DTS link; three-level DTS transmitter circuit; transmitted signal energy; two-level DTS architecture; word length 6 bit; Bandwidth; Clocks; Computer architecture; Jitter; Receivers; Transistors; Transmitters;
Conference_Titel :
Multiple-Valued Logic (ISMVL), 2012 42nd IEEE International Symposium on
Conference_Location :
Victoria, BC
Print_ISBN :
978-1-4673-0908-0
DOI :
10.1109/ISMVL.2012.16
