FPGA implementation of fast FIR low pass filter for EMG removal from ECG signal

This paper presents the hardware implementation of fast FIR low pass filter for Electromyogram (EMG) removal from Electrocardiogram (ECG) signal. We designed the architecture having less critical delay then convention FIR design and fast enough to remove EMG from ECG signal. We Proposed branched tree architecture for adder connection to reduce the critical delay. The Proposed architecture has been implemented on FPGA using Verilog Hardware Description Language (HDL). Since coefficient quantization technique is used, so this implementation consumes lesser area that reduces the Hardware consumption. We have used target device Virtex-5 (“xc5vlx110t-2-ff1136”), which is a preferred device in the field for modern Digital Signal Processing (DSP) applications.