• DocumentCode
    2299396
  • Title

    Hybrid floorplanning based on partial clustering and module restructuring

  • Author

    Yamanouchi, T. ; Tamakashi, K. ; Kambe, T.

  • Author_Institution
    Precision Technol. Dev. Center, Sharp Corp., Japan
  • fYear
    1996
  • fDate
    10-14 Nov. 1996
  • Firstpage
    478
  • Lastpage
    483
  • Abstract
    In this paper, we propose a hybrid floorplanning methodology. Two hierarchical strategies for avoiding local optima during iterative improvement are proposed: (1) Partial Clustering, and (2) Module Restructuring. These strategies work for localizing nets connecting small modules in small regions, and conceal such small modules and their nets during the iterative improvement phase. This method is successful in reducing both area and wire length in addition to reducing the computational time required for optimization. Although our method only searches slicing floorplans, the results are superior to the results obtained even with non-slicing floorplans. We applied our method to the largest MCNC floorplan benchmark example, ami49, and industrial data. For the ami49 benchmark, we obtained results superior to any published results for both estimated area and routing results.
  • Keywords
    circuit layout CAD; logic CAD; MCNC floorplan benchmark; ami49; area; computational time; floorplanning; iterative improvement; local optima; module restructuring; partial clustering; routing; slicing floorplans; Cost function; Genetic algorithms; Hardware design languages; Iterative methods; Joining processes; Optimization methods; Routing; Simulated annealing; Temperature; Wire;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer-Aided Design, 1996. ICCAD-96. Digest of Technical Papers., 1996 IEEE/ACM International Conference on
  • Conference_Location
    San Jose, CA, USA
  • Print_ISBN
    0-8186-7597-7
  • Type

    conf

  • DOI
    10.1109/ICCAD.1996.569866
  • Filename
    569866