Title :
Module placement on BSG-structure and IC layout applications
Author :
Nakatake, S. ; Fujiyoshi, K. ; Murata, H. ; Kajitani, Y.
Author_Institution :
Dept. of Electr. & Electron. Eng., Tokyo Inst. of Technol., Japan
Abstract :
A new method of packing rectangles (modules) is presented with applications to IC layout design. It is based on the bounded-sliceline grid (BSG) structure. The BSG dissects the plane into rooms associated with binary relations "right-to"and "above" such that any two rooms are uniquely in either relation. A packing is obtained through an assignment of modules on the BSG. Followed by physical realization BSG-PACK. A simulated annealing searches for a goon packing of all packings by changing the assignments. Experiments showed that hundreds of rectangles are easily packed in a small rectangle area (chip) with quite good quality in area efficiency. A wide adaptability is demonstrated specific to IC layout design. Remarkable examples are: the chip is not necessarily rectangle, L-shaped modules and modules which are allowed to partially overlap each other can be handled.
Keywords :
circuit layout CAD; integrated circuit layout; simulated annealing; IC layout design; adaptability; bounded-sliceline grid; packing rectangles; simulated annealing; Analog circuits; Application specific integrated circuits; Design automation; Design engineering; Information science; Integrated circuit layout; Printed circuits; Simulated annealing;
Conference_Titel :
Computer-Aided Design, 1996. ICCAD-96. Digest of Technical Papers., 1996 IEEE/ACM International Conference on
Conference_Location :
San Jose, CA, USA
Print_ISBN :
0-8186-7597-7
DOI :
10.1109/ICCAD.1996.569870