Study of the impact of charge-neutrality level (CNL) of grain boundary interface trap on device variability and P/E cycling endurance of 3D NAND flash memory

Poly-Si thin-film transistor (TFT) is the key building element for high-density 3D NAND Flash memory. Random grain boundary (GB) location and interface traps (Dit) density have been shown as the major root cause of variability [1]. However, with CNL pinned at midgap our previous model cannot adequately address experimental results - especially the cause of very low Vt TFT devices. In this work we point out that to accurately model the TFT device, CNL should not be restricted at the mid-gap only, as in the conventional assumption for Si/SiO2 interface trap, but should be randomly distributed inside the bandgap for GB trap. This makes donor-type Dit active besides the acceptor-type Dit. Simulation including the random CNL can well explain the very low-Vt devices and gives better TFT variability model. Furthermore, GB trap CNL plays an important role in governing the device subthreshold behavior during PE cycling for 3D NAND Flash.