Laser thermal anneal of polysilicon channel to boost 3D memory performance

Author

Lisoni, J.G. ; Arreghini, A. ; Congedo, G. ; Toledano-Luque, Maria ; Toque-Tresonne, Ines ; Huet, Karim ; Capogreco, E. ; Liu, L. ; Tan, C.-L. ; Degraeve, Robin ; Van den bosch, G. ; Van Houdt, J.

Author_Institution

Imec, Leuven, Belgium

fYear

2014

fDate

9-12 June 2014

Firstpage

1

Lastpage

2

Abstract

We have demonstrated that the engineering of Si channel grains in vertical 3D devices is of tremendous importance for read current, leading to up to 10 times higher ID, 3 times steeper STS slope, tighter ID and STS distributions, better channel-oxide interface, less defective grain boundaries and larger memory window. LTA arises as a potential candidate to engineer the Si channel microstructure. The limitations of LTA regarding crystallization depth can be overcome through complementary techniques such as substrate heating assisted LTA. This learning is crucial for the successful fabrication of advanced vertical devices stacks.

Keywords

annealing; grain boundaries; integrated memory circuits; laser materials processing; three-dimensional integrated circuits; 3D memory performance; Si; advanced vertical devices stack fabrication; channel grain engineering; channel microstructure engineering; channel-oxide interface; drain current; laser thermal annealing; polysilicon channel; read current; subthreshold swing; vertical 3D device; Annealing; Crystallization; Logic gates; Silicon; Substrates; Three-dimensional displays; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology (VLSI-Technology): Digest of Technical Papers, 2014 Symposium on

Conference_Location

Honolulu, HI

ISSN

0743-1562

Print_ISBN

978-1-4799-3331-0

Type

conf

DOI

10.1109/VLSIT.2014.6894346

Filename

6894346