An InGaAs/InP quantum well finfet using the replacement fin process integrated in an RMG flow on 300mm Si substrates

Author

Waldron, Niamh ; Merckling, C. ; Guo, Wenyong ; Ong, Patrick ; Teugels, Lieve ; Ansar, Sheikh ; Tsvetanova, Diana ; Sebaai, Farid ; van Dorp, D.H. ; Milenin, A. ; Lin, Dongyang ; Nyns, L. ; Mitard, J. ; Pourghaderi, Ali ; Douhard, B. ; Richard, O. ; Bende

Author_Institution

IMEC, Leuven, Belgium

fYear

2014

fDate

9-12 June 2014

Firstpage

1

Lastpage

2

Abstract

InGaAs FinFETs fabricated by an unique Si fin replacement process have been demonstrated on 300mm Si substrates. The devices are integrated by process modules developed for a Si-IIIV hybrid 300mm R&D pilot line, compatible for future CMOS high-volume manufacturing. First devices with a SS of 190 mV/dec and extrinsic gm of 558 μS/μm are achieved for an EOT of 1.9nm, L_g of 50nm and fin width of 55nm. A trade-off between off state leakage and mobility for different p-type doping levels of the InP and InGaAs layers is found and the RMG high-κ last processing is demonstrated to offer significant performance improvements over that of high-κ first.

Keywords

CMOS integrated circuits; III-V semiconductors; MOSFET; indium compounds; integrated circuit manufacture; quantum well devices; research and development; semiconductor doping; substrates; CMOS high-volume manufacturing; InGaAs-InP; R&D pilot line; RMG flow; RMG high-kappa last processing; Si; off state leakage; p-type doping levels; quantum well finFET; replacement fin process; size 1.9 nm; size 300 mm; size 50 nm; size 55 nm; Abstracts; FinFETs; Indium gallium arsenide; Indium phosphide; Logic gates; Silicon; Substrates;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology (VLSI-Technology): Digest of Technical Papers, 2014 Symposium on

Conference_Location

Honolulu, HI

ISSN

0743-1562

Print_ISBN

978-1-4799-3331-0

Type

conf

DOI

10.1109/VLSIT.2014.6894349

Filename

6894349