DocumentCode :
230354
Title :
Demonstration of fully functional 8Mb perpendicular STT-MRAM chips with sub-5ns writing for non-volatile embedded memories
Author :
Guenole Jan ; Thomas, L. ; Son Le ; Yuan-Jen Lee ; Huanlong Liu ; Jian Zhu ; Ru-Ying Tong ; Keyu Pi ; Yu-Jen Wang ; Dongna Shen ; Renren He ; Haq, Jesmin ; Teng, Jun ; Lam, V. ; Kenlin Huang ; Zhong, Tao ; Torng, T. ; Po-Kang Wang
Author_Institution :
TDK-Headway Technol. Inc., Milpitas, CA, USA
fYear :
2014
fDate :
9-12 June 2014
Firstpage :
1
Lastpage :
2
Abstract :
We present major breakthroughs in MTJ design for STT-MRAM applications allowing reliable write for pulse lengths down to 1.5ns, data retention up to 125°C for 10 years and full compatibility with BEOL process up to 400°C for 1 hour. We have successfully integrated the novel structure onto an 8Mbit test chip. We demonstrate writing of every single cell in the array using sub-5ns pulses over a wide temperature range without using any error correction. We also show that sensing times of 4ns are sufficient to read every data cell. The inherent scalability of the design makes it a prime candidate for universal embedded non-volatile memories down to the 28nm node and beyond.
Keywords :
MRAM devices; cache storage; magnetic tunnelling; semiconductor device manufacture; BEOL process; MTJ design; STT-MRAM chips; data cell; data retention; error correction; nonvolatile embedded memories; pulse lengths; test chip; time 1.5 ns; time 4 ns; universal embedded nonvolatile memories; Error correction codes; Magnetic tunneling; Memory management; Microprocessors; Temperature distribution; Writing; MRAM; data retention; embedded memory;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Technology (VLSI-Technology): Digest of Technical Papers, 2014 Symposium on
Conference_Location :
Honolulu, HI
ISSN :
0743-1562
Print_ISBN :
978-1-4799-3331-0
Type :
conf
DOI :
10.1109/VLSIT.2014.6894357
Filename :
6894357
Link To Document :
بازگشت