A highly scalable STT-MRAM fabricated by a novel technique for shrinking a magnetic tunnel junction with reducing processing damage

Author

Iba, Yoshihisa ; Takahashi, Asami ; Hatada, Akiyoshi ; Nakabayashi, Masaaki ; Yoshida, Chikako ; Yamazaki, Yasuyuki ; Tsunoda, Koji ; Sugii, Toshihiro

Author_Institution

Low-power Electron. Assoc. & Project (LEAP), Tsukuba, Japan

fYear

2014

fDate

9-12 June 2014

Firstpage

1

Lastpage

2

Abstract

A “shrink process” for reducing the size of a magnetic tunnel junction (MTJ) and mitigating the MTJ processing damage by using a sequence of oxidation and covering silicon dioxide (SiO₂) film after MTJ etching is proposed. Using the novel process, MR (magneto-resistance) ratio was improved more than 10% and junction size was able to be reduced to 20-nm diameter in a MTJ with processing size of 35-nm diameter and, as a result, the switching current was successfully reduced more than 60%.

Keywords

MRAM devices; etching; magnetic tunnelling; magnetoelectronics; magnetoresistance; oxidation; silicon compounds; MTJ etching; STT-MRAM; SiO₂; magnetic tunnel junction; magnetoresistance ratio; processing damage mitigation; shrink process; size 20 nm; size 35 nm; Etching; Films; Junctions; Magnetic tunneling; Oxidation; Resistance; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology (VLSI-Technology): Digest of Technical Papers, 2014 Symposium on

Conference_Location

Honolulu, HI

ISSN

0743-1562

Print_ISBN

978-1-4799-3331-0

Type

conf

DOI

10.1109/VLSIT.2014.6894365

Filename

6894365