Novel Critical Path Aware transistor optimization for mobile SoC device-circuit co-design

We present, for the first time, a holistic system-circuit-transistor co-optimization method, named “Critical Path Aware (CPA) transistor optimization”, through which we demonstrate power reduction of more than 20% in a state-of-the-art SoC design. In this method, we simplify and optimize all paths (critical and non-critical) to guide device design point for maximum power-performance benefit. We introduce novel `Binning and Mapping of statistical Path delay (BMP)´ method as a key enabler of this optimization platform, which deduces complex block level circuit data paths to a set of manageable ring oscillators, which are then used to link product level power-performance metric to transistor level optimization, taking intrinsic transistor performance, multiple Vt and multiple Lg into account simultaneously. This holistic optimization method has the potential as an important tool to extend Moore´s law beyond 10nm node by maximizing performance and minimizing process complexity.