DocumentCode
230418
Title
Physics based PBTI model for accelerated estimation of 10 year lifetime
Author
Zafar, Sameena ; Kerber, Andreas ; Muralidhar, R.
Author_Institution
IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA
fYear
2014
fDate
9-12 June 2014
Firstpage
1
Lastpage
2
Abstract
Threshold voltages (Vt) in high κ nFETs are observed to shift under prolonged positive gate bias stressing. This bias induced Vt shift (ΔVt) is referred as PBTI and is an important reliability issue. In this paper, we extend a previously proposed PBTI model to include de-trapping kinetics. The proposed model is verified by comparing calculated results with PBTI data measured over a wide range of stress conditions. Using the proposed model, an accelerated method for estimating 10 year lifetime is presented. This method does not require a-priori knowledge of parameters and uses a combination of voltage ramp and constant voltage measurements to estimate model parameters with the total measurement time <; 1 hour. Using these extracted parameters and the model equations, 10 year lifetimes are estimated at different stress voltages.
Keywords
field effect transistors; semiconductor device models; semiconductor device reliability; accelerated lifetime estimation; charge trapping; detrapping kinetics; high κ nFET; physics based PBTI model; positive gate bias stressing; time 10 year; Charge measurement; Logic gates; Numerical models; Stress; Time measurement;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology (VLSI-Technology): Digest of Technical Papers, 2014 Symposium on
Conference_Location
Honolulu, HI
ISSN
0743-1562
Print_ISBN
978-1-4799-3331-0
Type
conf
DOI
10.1109/VLSIT.2014.6894388
Filename
6894388
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