Title :
A 7-channel level generator chip for a VLSI digital tester
Author :
Sheehan, G. ; McGlinchey, G. ; Wilsher, K.
Author_Institution :
Analog Devices Inc., Wilmington, MA, USA
Abstract :
The automatic test equipment (ATE) level generator chip integrates all the per-pin analog levels required in a VLSI digital tester. This system chip was specified and defined at an architectural level by ATE engineers and implemented using a building block approach by the semicustom supplier working from standard function cells. The chip is integrated on an n-well junction-isolated merged bipolar-CMOS process build on a p wafer with a p epitaxial layer. BiCMOS has self-aligned polysilicon gate PMOS and NMOS devices and n-p-n, lateral, and vertical p-n-p devices. The process includes laser-trimmed thin film resistors and two-layer metal interconnect
Keywords :
BIMOS integrated circuits; VLSI; application specific integrated circuits; automatic test equipment; digital-analogue conversion; integrated circuit testing; signal processing equipment; ASIC; ATE; BiCMOS; D/A convertor; DAC; VLSI digital tester; automatic test equipment; building block approach; digital/analogue converter; laser-trimmed thin film resistors; level generator chip; merged bipolar-CMOS process; monolithic IC; n-p-n devices; n-well junction-isolated; p epitaxial layer; p wafer; per-pin analog levels; self-aligned polysilicon gate; semicustom; standard function cells; two-layer metal interconnect; vertical p-n-p devices; Calibration; Circuit testing; Clamps; Clocks; Integrated circuit testing; Logic devices; Multiplexing; Switches; Very large scale integration; Voltage control;
Conference_Titel :
Custom Integrated Circuits Conference, 1990., Proceedings of the IEEE 1990
Conference_Location :
Boston, MA
DOI :
10.1109/CICC.1990.124674
