Impact of contact and local interconnect scaling on logic performance

Author

Datta, Soupayan ; Pandey, Rashmi ; Agrawal, Ankit ; Gupta, Suneet K. ; Arghavani, R.

Author_Institution

Pennsylvania State Univ., University Park, PA, USA

fYear

2014

fDate

9-12 June 2014

Firstpage

1

Lastpage

2

Abstract

We perform a comparative analysis of metal-Si and metal-insulator-Si (MIS) contacts and quantify the impact of the contact/via resistances on logic performance. Our results show that silicide contacts account for 32% degradation in the ON current of an nFinFET (I_ON) compared to ideal contact. MIS contacts which lead to lowering of Schottky barrier height provide 12% performance gain at iso-energy. Technology scaling to 5 nm will make MIS contact contribute 35% to the overall extrinsic resistance, with metal resistance contribution rising to 20%.

Keywords

MOSFET; Schottky barriers; Schottky gate field effect transistors; electrical contacts; elemental semiconductors; interconnections; silicon; MIS contact; ON current degradation; Schottky barrier height; Si; contact-via resistance; local interconnect scaling; logic performance; metal resistance contribution; metal-Si contact; metal-insulator-Si contact; nFinFET; overall extrinsic resistance; silicide contact; Contact resistance; Metals; Resistance; Schottky barriers; Silicides; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology (VLSI-Technology): Digest of Technical Papers, 2014 Symposium on

Conference_Location

Honolulu, HI

ISSN

0743-1562

Print_ISBN

978-1-4799-3331-0

Type

conf

DOI

10.1109/VLSIT.2014.6894406

Filename

6894406