Coupling aware energy-efficient data scrambling on memory-processor interfaces

The improvement in security application has lead to the development of hardware cryptography. These crypto-processors are prone to security attack based on observing their power dissipation profile. One of the ways to combat this problem is to introduce randomness in the data. Bus scrambling is one of the ways to introduce non-determinism. But scrambling the data increases the power dissipation on bus drastically. One of the ways to reduce power is to encode the data off chip on the bus effectively. Existing work in the literature has focused on combining Bus Scrambling and encoding the data considering the dominance of self capacitance. So these methods fail in DSM technology where the coupling capacitance or inter-wire dominates the self capacitance. So this paper focuses on minimizing the power due to scrambling of data in cryptography applications by encoding the data on the bus in DSM technology. The encoder and decoder are designed using Magma Tools with 130 nm CMOS technology.