DocumentCode :
2305681
Title :
A novel high-speed binary and gray Incrementer/Decrementer for an address generation unit
Author :
Veeramachaneni, Sreehari ; Avinash, Lingamneni ; Kirthi, K.M. ; Srinivas, M.B.
Author_Institution :
Centre for VLSI & Embedded Syst. Technol., Int. Inst. of Inf. Technol.-Hyderabad, Hyderabad
fYear :
2007
fDate :
9-11 Aug. 2007
Firstpage :
427
Lastpage :
430
Abstract :
An incrementer/decrementer (INC/DEC) is a common building block in many digital systems like address generation unit which are used in microcontrollers and microprocessors. In this paper, novel architectures and designs for binary and gray INC/DECs are presented which faster than the existing ones without compromising in terms of power. The proposed architectures lay an emphasis on the usage of hybrid logic, that is, coupling of transmission gate with CMOS gates at appropriate stages for efficient design. Also, efficient utilization of the output and its complement, available in all existing implementations of gates, is done by using multiplexers in the proposed gray INC/DEC. For a 32-bit input, the proposed binary and gray INC/DEC achieve an improvement of 47%, 33% in delay and reduction of 38%, 28% in power-delay product respectively.
Keywords :
adders; microprocessor chips; CMOS gates; address generation unit; digital systems; gray incrementer-decrementer; high-speed binary; hybrid logic; microcontroller; microprocessors; transmission gate; Adders; CMOS logic circuits; Couplings; Delay; Digital systems; Information systems; Logic design; Microcontrollers; Microprocessors; Power dissipation;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Industrial and Information Systems, 2007. ICIIS 2007. International Conference on
Conference_Location :
Penadeniya
Print_ISBN :
978-1-4244-1151-1
Electronic_ISBN :
978-1-4244-1152-8
Type :
conf
DOI :
10.1109/ICIINFS.2007.4579215
Filename :
4579215
Link To Document :
بازگشت